ONKYO ds575dsp 01 free download

File name ds575dsp_01.pdf

Part 1 TX-DS575 TX-DS575X TX DS575 / TX DS575X Analog Processing Pin 31 and 32 balanced input for Right channel(RED); Pin 29 and 30 balanced input for Left channel ( p g ( ) p (GREEN) ) Q8501 have combination of ADC and DAC. Pin 29 ~32 are balanced inputs to ADC. Internaly the analog signal g goes through High Pass Limiter before it is clocked to L/R out. g g Master Clock MCK02 is made available from at Pin 39. Source of MCK02 is Q114. Pin 9 provides a serial audio data output derived from the analog inputs 29~32 whose data rate is dependant on L/R Clock at Pin 5 and Master Clock at Pin 39. The L/R clock and Serial Data may look alike except Pin 9 has data incorpoarted within the L/R clock. Pin 9 serial data will arrive at Q114 at Pin 8. "The analog signal that goes in at Pin 29~32 does not The 29 32 Q101 services as inverting amplifier come come out as analog through Pin 23~28 before it 23 28 While Q102 non inverting. Note correction has a c a ce o be g p ocessed as abo e as chance of being processed above" On PIN 5,6,. 6 6 5 5 TX-DS575 TX-DS575X TX DS575 / TX DS575X Analog Processing Audio Data f from Q8501 Pin 9 arrives at Pin 8 of Q114. Q fQ Part 2 Same data will find its way out at pin 20 of Q114. It is important X0-XI Pin 5 and Pin 6 work correct and that 12 2Mhz X0 XI 5,and 12.2Mhz oscilation is present No noticable drift or Jitter should be noticed present. noticed. TX-DS575 / TX-DS575X ANALOG PROCESSING Part 3 Analog Digital Q114 Pin 15 = L =H H Q114 Pin 17 = H =L It is conditional that audio data is present at Pin 8 (DAUX) of Q114 and that X-tal X103 is ON in-order for Q114 to operate properly The digital condition set forth at Pin 15 and 17 along a precence of digita data properly. at Pin 13, 12 and 11 will turn OFF X103. 4.6vdc Q114 waveforms when input is analog.